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Principal Logic Design Engineer – UALink IP/Subsystem at Astera Labs - ApplyBlast

Principal Logic Design Engineer – UALink IP/Subsystem

Astera Labs

1 month ago

4.3 on Glassdoor

Bengaluru, Karnataka, India

Onsite

Full Time

Senior

0 applicants

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About this role

Astera Labs is seeking a Principal Logic Design Engineer with 10–15 years of experience to lead the RTL and microarchitecture development for UALink-based IP and subsystems. The role involves translating protocol requirements into scalable hardware architecture, designing high-bandwidth data paths, and defining interfaces between UALink and other SoC components. This position requires strong expertise in high-performance interconnects, SystemVerilog, and computer architecture to drive design optimization and provide technical leadership.

Responsibilities

Lead architecture and RTL development for UALink IP/subsystems
Translate protocol and system requirements into scalable hardware architecture
Design high-bandwidth low-latency data paths and control logic

Skills

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

View Profile

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.