Principal Mixed Signal Design Verification Engineer

Astera Labs(17 hours ago)

San Jose, CAOnsiteFull TimeSenior$89,000 - $125,000Engineering

About this role

Astera Labs is seeking Principal Design Verification Engineers to support verification of high-speed SerDes/silicon products for Server, Storage, and Networking applications. The role involves developing and executing verification plans, working with hybrid environments, and collaborating with RTL designers.

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Required Skills

SystemVerilog
UVM
C/C++
Scripting
Verification

About Astera Labs

asteralabs.com

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.

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