Principal Timing Engineer

This role is for an experienced ASIC Design Engineer specializing in post-RTL design flows, specifically focusing on Synopsys or Cadence tools for SerDes IP solutions ranging from 10Gbps to 224Gbps. The position requires extensive knowledge of physical design, timing closure, and DFT generation to support Marvell's diverse product lines. Candidates will collaborate with analog and digital teams to deliver competitive mixed-signal solutions and support both pre- and post-silicon activities.