Sr. Staff Engineer, Digital IC Design
Marvell Technology
About this role
As an ASIC Design Engineer at Marvell, you will be responsible for the post-RTL design flow, which includes block and chip level synthesis, timing closure, DFT generation, and ECOs. This role involves collaborating with Analog/Digital design teams to deliver competitive SerDes IP solutions across various Marvell product lines, contributing to the design methodology, and supporting both pre and post-silicon activities.
Skills
Qualifications
About Marvell Technology
marvell.comDesigned for your current needs and future ambitions, Marvell delivers the data infrastructure technology transforming tomorrow’s enterprise, cloud, automotive, and carrier architectures for the better.
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About Marvell Technology
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Leadership Team
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
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Salary
$145k – $196k
per year