Sr. Staff Engineer, Digital IC Design
Marvell Technology(1 month ago)
About this role
As an ASIC Design Engineer at Marvell, you will be responsible for the post-RTL design flow, which includes block and chip level synthesis, timing closure, DFT generation, and ECOs. This role involves collaborating with Analog/Digital design teams to deliver competitive SerDes IP solutions across various Marvell product lines, contributing to the design methodology, and supporting both pre and post-silicon activities.
Required Skills
- ASIC Design
- Synthesis
- Timing Closure
- DFT Generation
- Static Timing Analysis
Qualifications
- Master's in Electrical Engineering
- PhD in Electrical Engineering
- 6+ Years Experience
About Marvell Technology
marvell.comDesigned for your current needs and future ambitions, Marvell delivers the data infrastructure technology transforming tomorrow’s enterprise, cloud, automotive, and carrier architectures for the better.
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