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infineon
This role focuses on performing RTL-to-gate synthesis and Static Timing Analysis to generate optimized gate-level netlists and ensure timing closure. The position involves collaborating with cross-functional teams to resolve timing issues, run constraint checks, and document key findings. It requires expertise in timing convergence, ECOs, and physical design optimization to support advanced hardware engineering projects.
Infineon Technologies is a global semiconductor company that delivers chips and system solutions for automotive, industrial, IoT, and consumer markets. Its product portfolio includes microcontrollers, sensors, power-management ICs and power semiconductors (e.g., MOSFETs/IGBTs), memories, connectivity (USB, Bluetooth, Wi‑Fi), LED drivers, security controllers and radiation‑hardened devices. Infineon focuses on energy efficiency, safety and security to enable applications from electric vehicles and industrial drives to smart-home and IoT devices. OEMs and system designers choose Infineon for its integrated hardware/software solutions, reliability, and global support.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for infineon.
infineon didn’t post a salary, so this is our estimate from similar listings.
Right around the average for this role
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