Staff/ Sr Staff Engineer, STA

Renesas is seeking a seasoned Backend Design Expert specializing in Static Timing Analysis (STA) and Logic Synthesis to own RTL-to-Gate conversion, constraint development, and final timing closure. The role focuses on optimizing physical-aware synthesis flows and achieving maximum performance at the lowest possible power and area for complex semiconductor designs. This position requires extensive experience in multi-mode and multi-corner timing closure, low-power implementation, and cross-functional collaboration to ensure design convergence.