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Senior ASIC Design Verification Engineer at Hewlett Packard Enterprise - ApplyBlast

Senior ASIC Design Verification Engineer

Hewlett Packard Enterprise

5 months ago

4.8 on Glassdoor

Bengaluru, Karnataka

Onsite

Full Time

Senior

0 applicants

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About this role

A Senior ASIC Design Verification Engineer at Hewlett Packard Enterprise drives advanced verification using UVM methodology to validate complex ASIC features, architect and develop verification environments, and perform verification using simulation tools.

Responsibilities

Drive advanced verification using UVM methodology to validate complex ASIC features
Architect and develop block, subsystem, and full-chip verification environments
Define, design, and execute verification plans and test suites for ASICs
Perform verification using simulation tools
Own end-to-end verification of large ASIC blocks

Skills

Qualifications

B.E/B.Tech or M.E/M.Tech in Electronics or related field

About Hewlett Packard Enterprise

hpe.com

Headquarters

The Woodlands, Texas, United States

Company Size

10001+ employees

Founded

1939

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Discover HPE edge-to-cloud, enterprise compute IT, data, and security solutions. Learn how HPE empowers digital transformation through AI and sustainability.