Senior Digital Verification Engineer

The Senior Digital Verification Engineer leads the development and execution of robust, reusable UVM verification environments to ensure functional coverage and first-silicon success for high-performance ASIC designs. The role involves driving verification strategy, automating large-scale regression flows, and mentoring the verification team to safeguard product quality. Key responsibilities include building scalable test-bench architectures, integrating Cadence verification tools, and collaborating cross-functionally to close verification gaps before RTL freeze.