Senior Group Technical Architect

This role involves owning full-chip Static Timing Analysis (STA) signoff across all process, voltage, and temperature corners and modes. The position requires driving timing closure at the chip level, managing constraints, and resolving violations using industry-standard tools like Synopsys PrimeTime and Cadence Tempus. Responsibilities include leading signoff methodologies, performing deep analysis on critical paths and clock domain crossings, and ensuring zero or near-zero timing violations at tapeout.