Senior Layout Engineer

This role involves owning the layout for high-speed analog and mixed-signal electronic ICs (EICs) and photonic ICs (PICs) for optical interconnects used in AI data centers. The position requires expertise in physical closure, parasitic-aware design, and EIC-PIC integration, while also supporting photonic layout and establishing layout methodologies for the Singapore team. The engineer will collaborate with design teams across the US, India, and Singapore to ensure successful tape-outs and silicon performance.