Altera
As a Physical Design Engineer at Altera, you will lead backend implementation flows for FPGA and SoC devices, managing tasks from netlist to GDSII tape-out. You will optimize performance, power, and area while collaborating with architecture, CAD/EDA, and manufacturing teams to meet strict technical constraints. The role involves developing automation frameworks, performing sign-off verification, and ensuring designs are manufacturable for high-volume production.
Headquarters
San Jose, California, United States
Company Size
1001-5000 employees
Founded
1983
Altera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.
5% above the average for this role
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