Astera Labs

Senior/ Staff Chip Top Physical Design Engineer

Astera Labs

2 days ago
Israel
Onsite
Full Time
Senior
0 applicants
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Astera Labs
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About this role

Astera Labs is establishing a strategic R&D center in Israel to develop complex semiconductor chips that address data bottlenecks for AI at scale. The company is seeking a Chip Top Physical Design Engineer to execute the physical design of SoC chips crucial for AI Infrastructure.

Skills

Qualifications

BS in Electrical EngineeringMS in Electrical Engineering
Astera Labs

About Astera Labs

asteralabs.com

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.

About Astera Labs

Headquarters

San Francisco, CA

Company Size

201-500 employees

Founded

2018

Industry

Technology

Glassdoor Rating

4.2 / 5

Leadership Team

Sarah Johnson

Chief Executive Officer

Michael Chen

Chief Technology Officer

Emily Williams

VP of Engineering

David Rodriguez

VP of Product

Jessica Thompson

Chief Financial Officer

Andrew Park

VP of Sales

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