Senior/Staff PLL Designer

Samsung Semiconductor Inc. is seeking a Senior/Staff PLL Designer to design and develop high-performance PLL and clocking subsystems for RF transceivers, SerDes, and high-speed I/O applications. The role involves working with advanced deep-submicron CMOS technologies, performing system modeling, and collaborating with digital and software developers to meet system requirements. Candidates must have extensive experience in frequency synthesizer and clock generation circuit design.