(Sr.) Staff Package Design Engineer - MIS Substrate/FC Expose Die (Experienced in Power or GaN Is Required)

The role involves designing and developing package and interconnect methods for power SiP/modules, wafer-level, flip-chip, and multi-chip module packaging, with a focus on qualification and optimization of materials, processes, and assembly partners. The engineer will collaborate with product groups, reliability, marketing, quality, and operations to ensure smooth production transitions and address customer concerns.