Staff Digital Design Engineer
Innatera(26 days ago)
About this role
The Staff Digital Design Engineer at Innatera is responsible for architecting, designing, and implementing digital IP blocks and subsystems for neuromorphic SoCs. This role involves translating high-level requirements into RTL specifications using SystemVerilog/Verilog, as well as collaborating with verification and backend teams to ensure alignment with design intent. The engineer will also optimize power, performance, and area goals, develop automation scripts, and mentor junior engineers, all while driving innovation in the semiconductor industry for advanced AI applications.
Required Skills
- Architecting
- Designing
- Implementing
- Digital IP Blocks
- Subsystems
- RTL Specifications
- Microarchitectures
- Front-End Design
- RTL Coding
- SystemVerilog
+26 more
Qualifications
- 6+ years of hands-on ASIC digital design experience
- Strong expertise in front-end digital design, including Verilog/SystemVerilog RTL development and debugging
- Solid understanding of SoC architecture, bus interfaces, and IP integration flows
- Experience performing synthesis and static timing analysis (STA) and defining timing constraints
- Proven experience with Cadence tools and industry-standard EDA flows
- Strong understanding of low-power design techniques and PPA trade-offs
- Proficiency in Python and shell scripting for design flow development and automation
About Innatera
innatera.comInnatera is a technology company specializing in ultra-low power neuromorphic processors that enable advanced pattern recognition for sensor applications. Their innovative Spiking Neural Processor mimics brain-like processing mechanisms, allowing for efficient and rapid data interpretation with minimal energy consumption. By leveraging proprietary analog-mixed signal computing architecture, Innatera's solutions provide significant improvements in latency and privacy for various industrial applications. The company is committed to pushing the boundaries of sensing technology, enhancing the capabilities of devices in power-limited environments.