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Principal Engineer, STA at Astera Labs - ApplyBlast

Principal Engineer, STA

Astera Labs

4 months ago

4.3 on Glassdoor

Bengaluru, Karnataka, India

Onsite

Full Time

Senior

0 applicants

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About this role

A Principal Engineer, Static Timing Analysis at Astera Labs owns full-chip timing closure and signoff for complex AI connectivity silicon across advanced process nodes. This technical leadership role requires driving STA strategy, developing automated flows, and partnering with cross-functional teams to ensure first-pass success on next-generation system-on-chips.

Responsibilities

Own end-to-end full-chip STA signoff across multiple modes and corners
Drive timing convergence on advanced process nodes from floorplan to tapeout
Develop and automate STA flows using PrimeTime and related signoff tools
Mentor STA engineers and review timing reports and signoff collateral
Influence EDA vendor engagements and define organization-wide STA methodology

Skills

Qualifications

Bachelor's or Master's in Electrical Engineering10+ years in Static Timing Analysis

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

View Profile

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.