Staff Engineer, Digital IC Design

Marvell is seeking an ASIC Design Engineer to design, verify, and evaluate digital circuits for high-speed data communication ICs within the Connectivity Business Unit. The role focuses on developing specifications, micro-architecture, and RTL for PAM4 DSPs and PHY transceivers supporting 25Gbps to 224Gbps data rates. Candidates will engage in functional verification, synthesis, timing analysis, and post-silicon debug for cloud and AI infrastructure applications.