Staff/ Sr Staff/Principal Engineer, STA

Renesas is seeking a seasoned Backend Design Expert specializing in Static Timing Analysis (STA) and Logic Synthesis to own the RTL-to-Gate conversion and final timing closure. This role focuses on optimizing physical-aware synthesis flows and managing multi-mode, multi-corner timing scenarios to ensure maximum performance at the lowest power and area. The position requires extensive experience in constraint development, low-power implementation, and scripting to automate design flows.