Staff STA Engineer

About this role

Responsibilities

• Own full-chip STA signoff, including constraints development, timing setup, analysis, debugging, and closure at multiple PVT corners
• Develop, validate, and maintain SDC constraints, including false paths, multi-cycle paths, generated clocks, and mode/corner definitions
• Perform timing correlation and optimization across synthesis, APR (P&R), and signoff tools
• Analyze and resolve complex timing issues such as cross-clock domain timing, hold/setup violations, and on-chip variation
• Work closely with SoC designers to interpret timing architecture, pipeline strategies, clocking schemes, and interface timing budgets