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Staff/Principal Physical Design STA Engineer at Astera Labs - ApplyBlast

Staff/Principal Physical Design STA Engineer

Astera Labs

9 hours ago

4.3 on Glassdoor

Haifa, Haifa District, Israel

Onsite

Full Time

Senior

0 applicants

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About this role

Astera Labs is seeking a Staff/Principal Physical Design STA Engineer to join its new R&D center in Israel, driving the development of complex semiconductor chips for AI infrastructure. The role involves executing Static Timing Analysis (STA) flows and sign-off methodologies to ensure high-performance silicon meets aggressive timing targets. The engineer will collaborate with Architecture, Design, DFT, and Physical Design teams to optimize timing closure and improve design methodologies.

Responsibilities

Execute STA flow and sign-off methodologies for advanced semiconductor chips
Develop and optimize complex SDC constraints across multi-scenario environments
Analyze cross-chip clock distribution networks and apply margining techniques

Skills

Qualifications

B.Sc. in Electrical EngineeringB.Sc. in Computer Engineering

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

View Profile

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.