Synthesis & Front-End Implementation Engineer
NXP Semiconductors(19 days ago)
Pune, IndiaOnsiteFull TimeMedior$60,000 - $80,000Electrical Engineering
Apply NowAbout this role
This role involves translating RTL designs into optimized gate-level netlists for complex IP blocks, focusing on synthesis, timing, power, and area optimization within a collaborative team environment. The engineer will develop automation scripts, evaluate new tools, and work closely with design teams to ensure design performance and quality.
Required Skills
- Verilog
- SystemVerilog
- Tcl
- Python
- RTL Synthesis
- STA
- Power Analysis
- Formal Verification
- Digital Design
- Automation Scripting
Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- 2+ years of relevant experience in digital ASIC/SoC design
- Proficiency with industry-standard synthesis tools
- Strong understanding of static timing analysis
About NXP Semiconductors
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