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Verification Engineer at Cadence - ApplyBlast

Verification Engineer

Cadence

28 days ago

4.0 on Glassdoor

Austin, Texas, United States

Onsite

Full Time

Senior

0 applicants

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About this role

This role involves defining verification strategies and architectures for semiconductor designs, utilizing methodologies like UVM and SystemVerilog to create robust testbenches. The position requires leading technical efforts in test development, debugging, and coverage analysis while collaborating with cross-functional teams to ensure project success. Candidates will mentor junior engineers and manage verification timelines to meet critical deadlines.

Responsibilities

Define verification strategy and design scalable testbench architectures
Lead root-cause analysis of complex design bugs and implement fixes
Manage verification timelines and provide final technical sign-off

Skills

Qualifications

B.E.B.TechM.TechM.S.

About Cadence

cadence.com

Headquarters

San Jose, California, United States

Company Size

10001+ employees

Founded

1988

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Cadence is a company specializing in electronic design automation (EDA) software and engineering services for the semiconductor and electronics industries. Their tools enable design and verification of integrated circuits, systems on chips, and electronics systems, streamlining the development process for engineers and designers. With a commitment to innovation and excellence, Cadence empowers companies to enhance product performance and reduce time to market through advanced simulation, verification, and design tools.