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ASIC Design Engineer at Hewlett Packard Enterprise - ApplyBlast

ASIC Design Engineer

Hewlett Packard Enterprise

4 months ago

4.8 on Glassdoor

Bengaluru, Karnataka, India

Onsite

Full Time

Senior

0 applicants

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About this role

An ASIC Design Engineer at HPE's HPE-Juniper division architect and develop block-level verification environments using SystemVerilog and UVM for next-generation network access solutions. The role focuses on verifying large ASIC blocks through code and functional coverage analysis before tape-out while collaborating with logic designers and software developers to resolve bugs. Engineers will utilize front-end simulation tools and scripting languages to improve verification infrastructure for faster, denser systems.

Responsibilities

Architect and develop block-level verification environments using SystemVerilog and UVM
Define, code, and deliver verification suites for complex ASIC subsystems
Verify large ASIC blocks independently and perform gate-level simulation
Analyze code coverage and functional coverage to sign off blocks for tape-out
Develop Perl, Python, or shell scripts to enhance verification infrastructure

Skills

Qualifications

MSEEBSEE5+ years of engineering experience

About Hewlett Packard Enterprise

hpe.com

Headquarters

The Woodlands, Texas, United States

Company Size

10001+ employees

Founded

1939

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