ASIC Verification Engineer

This ASIC Verification Engineer role at HPE Networking focuses on architecting and developing block-level verification environments using SystemVerilog and UVM methodology for sub-systems and full chips. The position involves writing verification suites, utilizing front-end simulator tools like VCS and Xcelium, and achieving sign-off through code and functional coverage analysis. Candidates will also collaborate with logic and software teams to resolve bugs and automate verification infrastructure using scripting languages.