ASIC/SoC Verification Engineer

This role requires a candidate with 5 to 7 years of experience in the ASIC/SoC life cycle, specifically focusing on verification up to the tapeout stage. The position involves defining full chip testbench architectures, writing test plans, and developing reusable block-level and subsystem testbenches using SystemVerilog and UVM. Key activities include creating constrained-random and directed test cases, implementing functional coverage and assertions, and conducting gate-level simulations and regression analysis.