ASIC/SoC Verification Engineer

This role requires a candidate with 8 to 14 years of experience in ASIC/SoC design and verification, holding a Bachelor's or Master's degree in a related engineering field. The position involves defining verification strategies, developing full-chip test plans, and building reusable testbenches using SystemVerilog and UVM methodologies. The successful candidate will oversee verification closure, conduct gate-level simulations, and collaborate with hardware design teams to resolve bugs and ensure successful tape-outs.