Design Verification Lead

Powerlattice is seeking an experienced Design Verification Lead to spearhead verification activities for complex SoC and IP designs, developing scalable SystemVerilog-based environments and automated regression flows. This role involves driving functional verification from RTL through gate-level simulation, collaborating with cross-functional teams to resolve design issues, and providing technical leadership to a team of verification engineers. The position requires a deep understanding of digital design fundamentals, industry-standard protocols, and EDA tools to ensure comprehensive verification and coverage closure.