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Junior Physical Design Engineer at Astera Labs - ApplyBlast

Junior Physical Design Engineer

Astera Labs

4 months ago

4.3 on Glassdoor

Tel Aviv-Yafo, Israel

Onsite

Full Time

Junior

0 applicants

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About this role

As a Junior Physical Design Engineer at Astera Labs, you will join the founding backend team in Israel to establish technical standards and drive the physical implementation journey for complex AI infrastructure chips. This role involves owning tasks from synthesis through signoff, ensuring designs meet extreme performance targets for rack-scale connectivity solutions. You will collaborate cross-functionally to refine backend methodologies and leverage automation to optimize workflows for next-generation silicon.

Responsibilities

Execute physical implementation steps including synthesis, floorplanning, and placement
Own macro-level implementation with deep focus on complex routing strategies
Drive final stages of design integrity through rigorous timing and physical verification
Participate in defining and refining backend methodologies with tool automation
Collaborate with Architecture and DFT teams on advanced process node challenges

Skills

Qualifications

Bachelor's Degree in Electrical EngineeringKnowledge of RTL-to-GDS flowFamiliarity with 7nm and below technologiesExperience with STA, LEC, DRC, and EMIR

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

View Profile

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.