Physical Design Backend STA Engineer
NVIDIA(1 month ago)
About this role
A Static Timing Analysis (STA) Physical Design Engineer at NVIDIA's Networking team in Israel focuses on enabling high-speed, low-latency communication devices by ensuring timing convergence and quality across chiplet and package levels. The role contributes to industry-leading physical design efforts within a collaborative engineering environment and supports delivery from pre-layout models through signoff. This position is embedded in a fast-paced, innovative semiconductor team where individual contributions impact product performance.
Required Skills
- Static Timing Analysis
- PrimeTime
- Timing Closure
- SDC Generation
- Timing Debug
- RTL Collaboration
- Physical Design
- PNR
- Physical Verification
Qualifications
- B.Sc. in Electrical Engineering
- B.Sc. in Computer Engineering
About NVIDIA
nvidia.comNVIDIA invents the GPU and drives advances in AI, HPC, gaming, creative design, autonomous vehicles, and robotics.
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