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© All Rights Reserved. ApplyBlast.com
Altera
The Physical Design Engineer will implement custom IP and SoC designs from RTL through GDSII, handling synthesis, floorplanning, place and route, clock tree synthesis, timing analysis, and physical optimization. The role collaborates with architecture, RTL, DFT, verification, and methodology teams to deliver high‑quality silicon for next‑generation FPGA technologies.
Headquarters
San Jose, California, United States
Company Size
1001-5000 employees
Founded
1983
Altera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.
15% above the average for this role