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Principal Design Verification Engineer at Astera Labs - ApplyBlast

Principal Design Verification Engineer

Astera Labs

1 month ago

4.3 on Glassdoor

San Jose, California, United States

Onsite

Full Time

Senior

0 applicants

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About this role

Astera Labs is seeking a Principal Design Verification Engineer to lead functional verification of high-speed SerDes/PHY IP for AI infrastructure. The role involves architecting UVM-based verification environments, driving coverage closure, and collaborating with analog, digital, and SoC integration teams to ensure first-pass silicon success.

Responsibilities

Architect UVM‑based verification environments for SerDes/PHY IP
Lead coverage analysis and drive regression to achieve silicon sign‑off
Mentor junior verification engineers and collaborate cross‑functionally

Skills

Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, or related fieldMS in Electrical Engineering or Computer EngineeringPhD in Electrical Engineering or Computer Engineering

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

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Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.