Senior or Staff Design Verification Engineer

Powerlattice is seeking an experienced Design Verification Lead to spearhead verification activities for complex SoC/IP designs, developing scalable SystemVerilog-based verification environments and strategies. This role drives functional verification from RTL through gate-level simulation, collaborating closely with cross-functional teams to identify and resolve design issues. The position involves technical leadership, mentoring verification engineers, and optimizing regression flows using industry-standard EDA tools.