Senior/Staff PLL Designer

Samsung Semiconductor is seeking a Senior or Staff PLL Designer to develop high-performance PLL and clocking subsystems for RF transceivers, SerDes, and high-speed I/O applications. The role involves designing critical PLL building blocks, performing system-level modeling and noise analysis, and collaborating with cross-functional teams to deliver IP meeting performance targets. Candidates will also support silicon bring-up, characterization, and debug in the lab.