Altera
The Soft CPU Design Engineer will architect, design, and implement high-performance, area-efficient Soft CPU cores optimized for Altera FPGA architectures. This role focuses on maximizing performance, power, and area by leveraging FPGA-specific components like ALMs and memory blocks while driving synthesis and timing closure. The position involves shaping the future of embedded processor roadmaps, such as the RISC-V-based Nios V ecosystem, to enable flexible processing in programmable logic.
Headquarters
San Jose, California, United States
Company Size
1001-5000 employees
Founded
1983
Altera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.
30% above the average for this role