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© All Rights Reserved. ApplyBlast.com
Altera
The Sr. Debug Design Verification Engineer is responsible for pre-silicon system verification, including SoC, FPGA, and full chip design verification. The role involves creating test cases and testbenches using UVM methodology, defining verification strategies, and coordinating with cross-functional teams to achieve comprehensive coverage. The position focuses on verifying Design for Debug architectures and ensuring system performance through full application testing.
Headquarters
San Jose, California, United States
Company Size
1001-5000 employees
Founded
1983
Altera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.
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