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Staff Physical Design Engineer - SoC EMIR Engineer at Astera Labs - ApplyBlast

Staff Physical Design Engineer - SoC EMIR Engineer

Astera Labs

4 months ago

4.3 on Glassdoor

Tel Aviv-Yafo, Israel

Onsite

Full Time

Senior

0 applicants

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About this role

Astera Labs is seeking a Physical Design Engineer specializing in SoC EMIR to lead the development of complex semiconductor chips at its new strategic R&D center in Israel. The role involves owning backend power methodologies and ensuring the power robustness and reliability of high-performance connectivity silicon for AI and cloud environments. Candidates will perform SoC EMIR analysis to meet aggressive voltage drop and reliability targets in advanced FinFET process nodes.

Responsibilities

Perform IR drop and signal/power electromigration analysis for complex chips
Collaborate with physical design teams to ensure full power integrity
Partner with package design engineers on chip-package co-analysis
Analyze root causes of voltage drop violations and EM risks
Develop expertise in advanced FinFET node power and reliability challenges

Skills

Qualifications

Bachelor's degree in Electrical EngineeringMaster's degree in Electrical Engineering

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

View Profile

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.