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Staff/ Principal Design Verification Engineer at Astera Labs - ApplyBlast

Staff/ Principal Design Verification Engineer

Astera Labs

4 months ago

4.3 on Glassdoor

Tel Aviv-Yafo, Tel Aviv District, Israel

Onsite

Full Time

Senior

0 applicants

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About this role

Astera Labs is seeking a Staff/Principal Design Verification Engineer to help build its new R&D center in Israel, focusing on verifying high-performance digital blocks and full-chip designs for advanced AI semiconductor connectivity solutions. The role involves developing complex SystemVerilog/UVM verification environments, executing rigorous testing plans, and collaborating with design engineers to resolve hardware bugs and ensure 100% verification closure.

Responsibilities

Design and develop ASIC verification environments for unit-level and subsystem blocks
Implement functional coverage models to drive 100% verification closure
Collaborate with design engineers to identify and resolve complex hardware bugs
Develop SystemVerilog/UVM components including traffic generators and checkers
Apply scripting techniques using Python or Tcl to automate verification tasks

Skills

Qualifications

BS in Electrical Engineering5+ years of ASIC verification experienceMS in Electrical Engineering (Preferred)

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

View Profile

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.