Subsystem/SoC Level Verification Engineer

This role requires a Senior Verification Engineer with 12-15 years of experience specializing in Ethernet Subsystem and SoC level functional verification. The candidate will develop complex verification environments using System Verilog and UVM, create block/system level test plans, and debug test failures to identify root causes. Key responsibilities include working with Cadence/Synopsys tools, implementing constrained random verification, and managing code and functional coverage.