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Senior Design Verification Engineer at Astera Labs - ApplyBlast

Senior Design Verification Engineer

Astera Labs

4 months ago

4.3 on Glassdoor

Tel Aviv-Yafo, Israel

Onsite

Full Time

Senior

0 applicants

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About this role

Astera Labs is seeking a Senior Design Verification Engineer to establish its new R&D center in Israel, focusing on developing verification environments for high-performance AI semiconductor chips. This role involves creating SystemVerilog/UVM testbenches, driving functional coverage closure, and collaborating with design teams to resolve complex hardware bugs for next-generation connectivity solutions.

Responsibilities

Develop and maintain SystemVerilog/UVM verification environments
Implement functional coverage models to drive closure
Debug and resolve complex hardware bugs
Create traffic generators, monitors, and checkers
Collaborate with design engineers on root-cause analysis

Skills

Qualifications

Bachelor’s degree in Electrical EngineeringMaster’s degree in Electrical Engineering

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

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Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.