SoC Timing Constraints Lead

STMicroelectronics is seeking a skilled SoC Timing Constraints Lead with 10–14 years of experience to join their Digital Design Front-End team. The role involves developing digital IP-level and SoC constraints, ensuring constraints sanity, verification, and timing closure using industry-standard EDA tools. The ideal candidate will collaborate with cross-functional teams to optimize designs for performance, power, and area while supporting integration and bring-up activities.