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Altera
A Design Engineer at STA is responsible for the timing closure and signoff of FPGA/SoC and subsystem timing. The role involves performing static timing analysis, deriving interface timing constraints, and collaborating with design and physical design teams for timing convergence. Candidates must have experience with industry-standard EDA tools and tapeout processes in advanced technologies.
Headquarters
San Jose, California, United States
Company Size
1001-5000 employees
Founded
1983
Altera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.
Altera didn’t post a salary, so this is our estimate from similar listings.
42% below the average for this role
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