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Synthesis & STA Engineer – High-Speed SerDes at Astera Labs - ApplyBlast

Synthesis & STA Engineer – High-Speed SerDes

Astera Labs

1 month ago

4.3 on Glassdoor

San Jose, California, United States

Onsite

Full Time

Senior

0 applicants

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About this role

Astera Labs is seeking a Synthesis & STA Engineer to drive the planning, coordination, and execution of design activities for high-speed analog/mixed-signal SerDes and connectivity ASICs. The role involves end-to-end ownership of logic synthesis and static timing analysis across digital portions of mixed-signal SerDes PHY designs, ensuring robust timing closure at advanced nodes. This position requires deep technical expertise in mixed-signal integration and close collaboration with analog, RTL, physical design, and verification teams.

Responsibilities

Drive planning and execution of high-speed analog/mixed-signal SerDes design
Perform RTL synthesis and static timing analysis for digital controller blocks
Develop and validate SDC constraints and manage multi-mode multi-corner environments

Skills

Qualifications

Master's in Electrical Engineering or Computer Science

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

View Profile

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.