Staff Engineer - STA

A Digital Physical Design Engineer at NXP is responsible for complete static timing analysis (STA) signoff for System-on-Chip (SoC) or subsystem designs up to tapeout. The role involves writing and refining timing constraints, collaborating with frontend, DFT, and IP teams, and ensuring signal integrity closure across advanced technology nodes like 5nm. Candidates must possess leading capabilities in signoff functions and utilize AI tools to enhance STA activities.