STA Engineer
Astera Labs(1 month ago)
About this role
Astera Labs is expanding its R&D efforts in Israel and seeks a Tech Lead STA Engineer to develop and establish the timing sign-off methodology for advanced semiconductor chips supporting AI infrastructure. The role involves collaborating across design teams to ensure silicon performance meets high standards in data center environments.
Required Skills
- STA
- PAndR
- Timing Closure
- Scripting
- Automation
- Sign-off Methodology
- Constraint Development
- Physical Design
- Data Center
- Semiconductor
Qualifications
- BS in Electrical Engineering, Computer Engineering, or related
- 5+ years of STA experience
- Deep expertise in multi-scenario STA
- Experience with 7nm technology
- Knowledge of margining methodologies
About Astera Labs
asteralabs.comAstera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.
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