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Tech Lead STA Engineer at Astera Labs - ApplyBlast

Tech Lead STA Engineer

Astera Labs

1 month ago

4.3 on Glassdoor

Hyderabad, Telangana, India

Onsite

Full Time

Senior

0 applicants

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About this role

Astera Labs is seeking a Principal Engineer for Static Timing Analysis to lead top-level timing closure and signoff for next-generation AI connectivity silicon. This high-impact role involves driving full-chip STA strategy across advanced process nodes and collaborating with cross-functional teams to ensure first-pass timing success. The position offers ownership and influence over the development of complex SoCs powering rack-scale AI infrastructure.

Responsibilities

Own full-chip top-level STA signoff and timing closure for complex AI connectivity SoCs
Define and evolve STA methodology, constraints strategy, and signoff criteria across the organization
Partner with cross-functional teams to drive timing-aware design decisions from architecture through tapeout

Skills

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

View Profile

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.